The recent enhancement in the capability of computers makes the loss of time and power consumption when refreshing a memory, such as a DRAM (Dynamic Random Access Memory), unnegligible. Under the above circumstance, the refresh cycle is controlled such that the memory refresh is carried out at a long cycle in a state in which error (data error) occurs less while being carried out a short cycle in a state in which errors easily occur.
FIG. 18 is a diagram schematically depicting an example of a conventional operation manner to control a memory refresh cycle. The conventional operation manner of controlling a memory refresh controls the memory refresh cycle by monitoring error in a memory 91 through the use of a memory refresh circuit 90, as depicted in FIG. 18. For example, the memory refresh circuit 90 of FIG. 18 is configured to include a memory controller 92, an ECC (Error Correcting Code) circuit 93, an error rate monitor 94, a refresh cycle creating section 95, a refresh request creating section 96, and an external interface 97.
The memory controller 92 controls access to the memory 91, and, for example, carries out memory refresh and reads data from the memory 91 when data access is carried out.
The ECC circuit 93 generates, when writing data into the memory 91 under the control of the memory controller 92, an error detection/correction code (checking code) based on the data to be written, attaches the code to the data and writes the data into the memory 91. For example, when data is read from the memory 91 by the memory controller 92, the ECC circuit 93 checks validity of the data through use of the read data and the corresponding error detection/correction code and, if a correctable error is detected as an error, the error in the data is corrected. Then, the ECC circuit 93 notifies the presence/absence of error to the error rate monitor 94.
The error rate monitor 94 holds an amount of error occurrence, and for example, counts the “error number” (amount of error occurrence) on the basis of the presence/absence of errors notified by the ECC circuit 93. For example, the error rate monitor 94 holds a variable representing the “error number”, and decreases a predetermined value from the held number of errors when no error occurs while adding a predetermined values to the held “error number” when an error occurs.
The refresh cycle creating section 95 generates a refresh cycle. For example, the refresh cycle creating section 95 compares “error number” held by the error rate monitor 94 and a predetermined reference value (error rate), and shortens the refresh cycle when “error number” exceeds the reference value while lengthening the refresh cycle when “error number” is lower than the reference value.
The refresh request creating section 96 requests the memory controller 92 to carry out a refresh operation at the refresh cycle created by the refresh cycle creating section 95.
The external interface 97 carries out interface control of the processor of the information processing apparatus (not illustrated) incorporating therein the memory refreshing circuit 90 with an upper unit including another controller, and carries out interface control exemplified by reception of a read command or a write command from a processor, reply to the processor with read data, and transmission of memory status information to the processor.
Accordingly, in the conventional manner of controlling the memory refresh cycle, the ECC circuit 93 first of all detects an error in the memory 91 on the basis of the data that the memory controller 92 has read from the memory 91. Here, “error number” held by the error rate monitor 94 decreases when the ECC circuit 93 detects no error while increasing when the ECC circuit 93 detects an error. Then, when “error number” becomes lower than the reference value, the refresh cycle is adjusted to be longer and when the number of errors becomes more than the referenced value, the refresh cycle is adjusted to be shorter.
The Patent Reference 1 below discloses a technique in which an ECC circuit reads a number of data pieces and corresponding check bits at a regular refresh cycle, carries out error detection and correction, accumulates a first detection signal representing absence of errors, accumulates a second detection signal representing presence of errors which signal has a larger weight than that of the first detection signal so as to reduce the first amount of accumulation, and lengthens the refresh cycle when the accumulated amount exceeds a predetermined amount while shortening the refresh cycle when the accumulated amount comes to be lower than the predetermined amount.
Further, the Patent Reference 2 discloses a technique in which a refresh cycle is lengthened until an ECC circuit detects a correctable error, the optimum refresh cycle is set for each block, and the refresh cycle of an unused region is set to be infinity (i.e., no refresh operation is carried out on the region).    [Patent Reference 1] Japanese Patent Application Laid-Open (KOKAI) Publication No. 2002-025299    [Patent Reference 2] Pamphlet of WO96/28825
However, the above conventional operation manner of controlling a memory refresh frequency and the above Patent References 1 and 2 have to always detect an error in the entire memory. For this reason, in detection of an error occurring locally such as in a case where errors occur in some of the addresses in the memory, it takes long time a problem of low responsiveness to arise when the operational environment of the system temporarily varies.
In particular, since the Patent References 1 and 2 are technique of control predicted on control in the stand-by mode of the memory, the refresh cycle can be modified only in the stand-by mode, but cannot be dynamically modified during a normal operation. This causes a problem that the refresh cycle cannot be adjusted in harmony with the state of error occurrence in the memory.